Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/2118
Title: Technology for Faulty Blocks Coverage by Spares
Authors: Hahanov, Vladimir
Chumachenko, Svetlana
Litvinova, Eugenia
Zakharchenko, Oleg
Kulbakova, Natalka
Keywords: Blocks
Coverage by Spares
CLB
Issue Date: 2009
Publisher: EWDTS
Citation: Hahanov Vladimir Technology for Faulty Blocks Coverage by Spares /Hahanov Vladimir, Chumachenko Svetlana, Litvinova Eugenia, Zakharchenko Oleg, Kulbakova Natalka //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09)
Abstract: The technology for the minimum coverage of faulty blocks by spares when repairing the logic part of digital system-on-chip is proposed. The general provisions and rules of coverage for the matrix of configurable logic blocks (CLB) with faulty cells are considered. Coverage criteria for faulty cells are developed. Examples of the algorithm implementation are made. Billions of digital systems-on-chips, used in the world, containing up to 16 types of various components (processor, memory, logic, buses, dedicated computers), which can be divided into 2 subsets: the memory (90%) and logic (10%). At that faults, detected in memory, are repaired successfully by the onchip facilities of the leading companies (Virage Logic, Intel). But almost 10% of logic is unamenable to regular solutions in the on-chip repair. Today, the world's biggest problem in the market of electronic technology is repairing the logic part of digital system-on-chip. Due to high market appeal the problem of diagnosis and repair of memory and logic cells is considered in the paper. It is one of the Gartner's Top 10 Strategic Technologies for 2009 that is solved by readdressing faulty cells to faultless components from the spare rows, columns and tiles. The strategy works on the logic blocks, which must be addressed (and should be provided with repair blocks) or reprogrammable on the faultless space of the chip for the embedded repair. Repair models for SiP memory modules are considered in the papers [1-6]. It should also take into account that the level of sales of computers has fallen in the 2 quarter of 2009 by 8% and amounted to 66 million pieces, but sale of laptops has grown by 20%. With regard to market of chips, there is the highest rise of sales in the last 13 years. This fact confirms Moore's Law – transistor today is worthless, a user will pay for power. The whole world sees the future of digital systems-on-chips. Conclusion – all market-based ideas will be implemented in the chip with a dedicated functionality. So, Infrastructure IP creation in a chip is important problem, because it is capable to realize the embedded diagnosis and repairing, which will significantly improve the yield and extend the life cycle of digital product. Therefore, any new solution in this area might be interesting for the market of electronic technology, which determines the urgency of the proposed technology for quasi-optimal faulty blocks coverage by spare components. The papers [7-9] are devoted to the development of the theory and methods for optimization of geometric design, in particular, the research of optimization placement problem for rectangular objects. The optimization placement problem for rectangular objects with variable metric characterizations in a given area is considered in [7, 8]. The analysis of advanced technologies for embedded Functional Intellectual Property of digital system-in-package is shown in [10]. Features of the architecture «System-in-Package» and present repair strategies for digital systems-on-chips, as well as the method of evaluation the reliability of their performance are considered. The problem of SoC testing technologies adaptation to new digital system embodiment System-in-Package (SiP) that allows implementing on-chip sophisticated specialty computers and RF devices is considered in [10]. System-in-Package forms new objectives and goals of Infrastructure IP for real time SiP functionality, which differ from embedded SoC diagnosis essentially. Structure-logical diagnosis and repair methods for FPGA functional logic blocks based on real time fault detection table analysis are proposed. A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed in [10]. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns is realized. The objective of the research is the development of technology for the optimal faulty blocks coverage by spares when repairing the logic of digital SoC. Research tasks are: 1) The development of generalities and rules to cover the matrix of configurable logic blocks with faulty cells. 2) The development of coverage criteria for faulty cells. 3) Flowcharting for the bypassing the matrix of configurable logic blocks to obtain coverage. 4) Flowchart examples.
URI: http://openarchive.nure.ua/handle/document/2118
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