Metastability Testing at FPGA Circuit Design using Propagation Time Characterization

Abstract

This paper describes the measurement method and experimental technique with advanced instrumentation setup for analysing the metastability behavior and performance measurement of flip-flops used in programmable logic devices. In order to demonstrate this testing approach, the results for metastable characteristics parameters of one FPGA digital circuit fabricated commercially in 90 nm CMOS process are presented. The same test methods can also be used for evaluation of timing reliability in digital circuits as well.