Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1968
Title: Models for Embedded Repairing Logic Blocks
Authors: Hahanov, V. I.
Frolov, A.
Litvinova, E. I.
Tiecoura, Yves
Keywords: Models for Embedded
Repairing Logic Blocks
Issue Date: 2012
Publisher: EWDTS
Citation: Hahanov V. I. Models for Embedded Repairing Logic Blocks /Hahanov V. I., Litvinova E. I., Frolov A., Tiecoura Yves //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2012)
Abstract: The models of combinational circuits, focused on solving practical problems of embedded repairing components of the logic units are proposed. The logical circuit is complemented by operational and control automata for modeling digital devices, which increases processing time and hardware costs for creating a wrap of addressable elements. The structures can also be used for hardware modeling functionalities of digital projects by using PLD, which allows improving the performance of software model verification. The proposed solution of embedded gate repair for combinational circuits makes it possible to comprehensively solve the problem of autonomous repairing digital systems on chips due to the time and hardware project redundancy.
URI: http://openarchive.nure.ua/handle/document/1968
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

Files in This Item:
File Description SizeFormat 
Литвинова_EWDTS_2012.pdf2.37 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Admin Tools