Models for Embedded Repairing Logic Blocks

Публікація:
Models for Embedded Repairing Logic Blocks

dc.contributor.author	Hahanov, V. I.
dc.contributor.author	Frolov, A.
dc.contributor.author	Litvinova, E. I.
dc.contributor.author	Tiecoura Yves
dc.date.accessioned	2016-09-02T07:46:45Z
dc.date.available	2016-09-02T07:46:45Z
dc.date.issued	2012
dc.description.abstract	The models of combinational circuits, focused on solving practical problems of embedded repairing components of the logic units are proposed. The logical circuit is complemented by operational and control automata for modeling digital devices, which increases processing time and hardware costs for creating a wrap of addressable elements. The structures can also be used for hardware modeling functionalities of digital projects by using PLD, which allows improving the performance of software model verification. The proposed solution of embedded gate repair for combinational circuits makes it possible to comprehensively solve the problem of autonomous repairing digital systems on chips due to the time and hardware project redundancy.	uk_UA
dc.identifier.citation	Hahanov V. I. Models for Embedded Repairing Logic Blocks /Hahanov V. I., Litvinova E. I., Frolov A., Tiecoura Yves //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2012)	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1968
dc.language.iso	en	uk_UA
dc.publisher	EWDTS	uk_UA
dc.subject	Models for Embedded	uk_UA
dc.subject	Repairing Logic Blocks	uk_UA
dc.title	Models for Embedded Repairing Logic Blocks	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication