Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1965
Title: Method for Diagnosing SoC HDL-code
Authors: Zaychenko, S.
Hahanov, V.
Varchenko, V.
Keywords: Diagnosing
HDL
SoC
Issue Date: 2014
Publisher: EWDTS
Citation: Sergey Zaychenko Method for Diagnosing SoC HDL-code /Vladimir Hahanov, Sergey Zaychenko, Valeria Varchenko//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2014)
Abstract: This article describes technology for diagnosis SoC HDL-models, based on Code-Flow Transaction Graph. Diagnosis method is focused to decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analysis the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis. The goal is creation TAB-matrix model (Tests – Assertions – Blocks functional) model and diagnosis method to decrease the time of testing and memory for storage by means of forming ternary relations (test – monitor – functional component) in a single table. The problems are: 1) development of digital system HDL-model in the form of a transaction graph for diagnosing functional blocks by using assertion set; 2) development method for analyzing TABmatrix to detect minimal set of fault blocks; 3) Synthesis of logic functions for embedded fault diagnosis procedure.
URI: http://openarchive.nure.ua/handle/document/1965
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

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