Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1952
Title: Early Detection of Potentially Non-synchronized CDC Paths Using Structural Snalysis Technique
Authors: Zaychenko, Sergey
Melnik, Dmitry
Lukashenko, Olga
Keywords: Early Detection
CDC
Structural Snalysis Technique
Issue Date: 2009
Publisher: EWDTS
Citation: Sergey Zaychenko Early Detection of Potentially Non-synchronized CDC Paths Using Structural Snalysis Technique/Dmitry Melnik, Olga Lukashenko, Sergey Zaychenko//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09)
Abstract: The number of independent clock domains found on the typical today's device is continuously growing. According to the latest industry research, the average number of clock domains on a single device is >15-20 and it becomes higher and higher from day to day. The CDC-related design flaws are also growing exponentially, appearing to be very dangerous as the roots of intermittent chip failures (can be found only in the silicon). Static CDC verification is considered as one of the first de-facto steps in today's SoC design methodology; only static techniques can work as soon as the RTL starts taking shape. This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis. The sections of logic elements that driven by clocks coming from different sources are called clock domains. The signals that interface between asynchronous clock domains are called the clock domain crossing (CDC) signals. The DATA_A signal is considered as an asynchronous signal into the receiving clock domain (no constant phase and time relationship exists between CLK_A and CLK_B).The nature of CDC bugs is intermittent; it simply means that a test suite can be successfully completed on a chip in the morning, but the same tests will complete with errors for the same chip in the afternoon. Consider the simplest flip-flop example: such a flip-flop is located anywhere in the chip; the data signal for this flip-flop comes from the domain #A but the clock signal — from the domain #B... so whenever the setup or hold condition is violated, the flip-flop can go to one or to zero and it cannot be predicted.
URI: http://openarchive.nure.ua/handle/document/1952
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