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Title: Pattern Overlapping - a Promising Compression Method for Narrow Test Access Mechanism SOC Circuits
Authors: Novak, O.
Jenícek, J.
Keywords: Memory management
Circuit testing
Issue Date: 2008
Publisher: ХНУРЭ
Citation: Novak, O. Pattern Overlapping - a Promising Compression Method for Narrow Test Access Mechanism SOC Circuits / O. Novak, J. Jeníče / Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 1. – С. 26-33
Abstract: This paper describes research results obtained in the field of test pattern compression and decompression. We refer the hardware test pattern decompression system DyRESPIN built-in on a System on Chip, which uses test patterns compressed by the compressing algorithm called OMPAS. COMPAS reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. We report improvements that have been done recently on COMPAS. COMPAS algorithm has to manipulate with enormous amount of data when compressing test sets of large circuits and the CPU time grows rapidly with the growing number of test vectors. The CPU time problem was solved by using a test vector initial encoding by sparse vectors and by using a dynamic structure for storing the precalculated parameters of candidate vectors to be used in the near future algorithm loops for overlapping with the actual scan chain content. This arrangement allows the algorithm to skip unnecessary computations. The improvements cause that the CPU time grows approximately linearly with the size of the tested circuit. DyRESPIN uses a built-in processor for test control, the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams and the FPGA part of the chip for the wrapped cores implementation. The highly compressed test vectors are transferred from the memory to those selected cores that are reconfigured into the embedded tester cores. The patterns are decompressed within the internal scan chains of the embedded tester cores and they are simultaneously fed into the parallel scan chains of the cores under test with the help of the Test Access Mechanism (TAM) and standard wrappers. After having tested the first cores under test the TAM of the SoC is partially reconfigured with the help of the partial reconfiguration bitstreams stored in the RAM memory and the till now untested cores are tested by those cores that start to serve as embedded testers.
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