Please use this identifier to cite or link to this item:
|Title:||Malicious Hardware: characteristics, classification and formal models|
|Keywords:||Integrated circuit modeling|
|Citation:||Gorbachov V. Malicious Hardware: characteristics, classification and formal models / V. Gorbachov // IEEE East-West Design & Test Symposium (EWDTS2014), Kiev, Ukraine, KhNURE, 2014, pp. 254-257.|
|Abstract:||Electronic Systems (ES) that contain embedded malicious hardware represent a serious threat, especially for government, aeronautic, financial and energy system applications. MHs can be implemented as hardware modifications to application specific ICs (ASICs), microprocessors, digital signal processors, or as IP core modifications for field programmable gate arrays (FPGA) . They are able to turn off the CPU, to send confidential information and bypass the software user authentication mechanisms. There are some important characteristics of this type of threat: standard testing methods, such as the common functional verification and Automatic Test Pattern Generation (ATPG) cannot always be used to solve the problem of detecting MH , ; identification of the threat sources without special tools is practically impossible; even in cases when an information security violation is detected, it is very difficult to prove that this action was performed by MH. These and other features make MHs very promising embedded devices for planning of electronic terrorism. Therefore, detecting and preventing approaches are in the attention centre of IT systems security investigation.|
|Appears in Collections:||Кафедра електронних обчислювальних машин (ЕОМ)|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.