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|Title:||The Method of Fault Backtracing for HDL - Model Errors Searching|
HDL - model
|Citation:||Kucherenko Dariya The Method of Fault Backtracing for HDL - Model Errors Searching /Yevgeniya Syrevitch, Andrey Karasyov, Dariya Kucherenko//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09)|
|Abstract:||In this paper the method of design error searching in non-structured HDL-code was considered. The method of backtracing was developed. An experiment on HDLmodel of digital device using this method was carried out. In modern CAD tools the basic way of device description is usage of hardware description languages, i.e. VHDL or Verilog, which allow making SOC design process faster. World companies – vendors of digital circuits, are forced to decrease their time-tomarket. Verification of digital projects, that is hardware or built-in hardware-software systems described in a Hardware Description Language - HDL, is the important task during designing digital devices. Often more than 70% of development time is spent on search and correction of mistakes in the project. Process of diagnosing is based on: DD model, allowing carrying out tests generation; designing errors, characteristic for HDL-models; algorithm of tests generation; methods of design errors search. Within the framework of technical diagnostics methods, there are several algorithms of defects search: based on available tests and known function of the device (functional algorithms on the base of errors tables or functions of errors tables), and based on the structure of the device (structural algorithms on the base of a reachability matrix). The purpose of the given work is to develop methods of defects/errors search in a non-structured HDL-code, allowing to reduce time of carrying out of diagnostic experiment and to reduce length of the diagnosis. Proceeding from the aforesaid, it is necessary to solve a task of adaptation of the method of backtracing at verification of HDL-models and to carry out diagnostic experiments on defect/design error search within the framework of verification.|
|Appears in Collections:||Кафедра автоматизації проектування обчислювальної техніки (АПОТ)|
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