Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/2114
Title: SUM IP Core Generator – Means for Verification of Models-Formulas for Series Summation in RKHS
Authors: Hahanov, Vladimir
Chumachenko, Svetlana
Skvortsova, Olga
Melnikova, Olga
Keywords: Means
Verification
SUM IP Core Generator
RKHS
Issue Date: 2006
Publisher: EWDTW
Citation: Hahanov Vladimir SUM IP Core Generator – Means for Verification of Models-Formulas for Series Summation in RKHS /Vladimir Hahanov, Svetlana Chumachenko, Olga Skvortsova, Olga Melnikova //Proceedings of IEEE East-West Design & Test Workshop (EWDTW’06)
Abstract: Program system SUM IP Core Generator – means for verification of models – formulas of series summation in Reproducing Kernel Hilbert Space (RKHS) which allows to carry out input of the description of the model-formula with the help of the GUI-interface is offered; to model models – formulas with the help of software products Mathematica, Sinplify, Modelsim, Riviera, Active HDL; to generate initial files IP-core in languages of the description of equipment VHDL, Verilog, System C; to generate scripts – files for modelling, synthesis, implementation, time modelling; to synthesize tests, parameters, conditions for verification on basis Testbench; to carry out post-synthesis modelling for revealing mistakes in codes. The program system SUM IP Core Generator is proposed. Its structure is represented on Fig. 1. The Purpose of this system is essential reduction of time for data preparation by use of the user-friendly GUI-interface with a view of the subsequent modelling for definition of adequacy and accuracy of modelsformulas, and also automatic generation of the HDLcode considered in quality IP Сore. Solved problems (see fig. 1): 1. Input of the description of the model-formula with the help of the GUI-interface. 2. Modelling models-formulas with the help of software products Mathematica, Sinplify, Modelsim, Riviera, Active HDL. 3. Generation of initial files IP-core in languages of the description of equipment VHDL, Verilog, System C. 4. Generation of scripts-files for modelling, synthesis, implementation, time modelling. 5. Synthesis of tests, parameters, conditions for verification on the basis of generating Testbench. 6. Post-synthesis modelling for revealing mistakes in codes.
URI: http://openarchive.nure.ua/handle/document/2114
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