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Title: Path Sensitization at Functional Verification of HDL-Models
Authors: Shkil, Alexandr
Syrevitch, Yevgeniya
Karasyov, Andrey
Cheglikov, Denis
Keywords: functional verification
graph model
path sensitization
distinguishing sequences
Issue Date: 2006
Publisher: EWDTW
Citation: Yevgeniya Syrevitch Path Sensitization at Functional Verification of HDL-Models /Alexandr Shkil, Yevgeniya Syrevitch, Andrey Karasyov, Denis Cheglikov //Proceedings of IEEE East-West Design & Test Workshop (EWDTW’06)
Abstract: Strategy of verification of digital devices models, represented in hardware description languages, is considered. The basic idea is in using path sensitization method in a graph model, generating distinguishing tests for separate functional elements, superposing these tests and interactive calculating etalon reactions. The necessity of researches in the field of verification is caused by the lack of effective methods and tools of functional verification of digital devices (DD) models on a step of describing them on behavioral level. World companies – vendors of digital circuits, are forced to decrease their time-to-market. According to vendors’ evaluations, verification (functional as well) takes up to 80% of labor expenditures in the design cycle. There is a big demand for tools of functional verification of devices models on a step of their description in hardware description language (HDL) on behavioral level. If model description in hardware description languages (HDL) is considered as a software program, then, from one point of view it is necessary to execute software verification, but the other point of view it is not always optimal. Software verification considers all modes with all data testing. While checking correspondence between code, which describes a device, and its specification on all possible data for all reachable inputs, to hold on verification during appropriate time with 100% completeness it is not possible. Assume that all in-build operators are combinational elements. It means that to check them it is necessary to drive 2n values, where n – total dimension of inputs. To get high quality of verification for appropriate time it is necessary to decrease number of driven tests. Despite variety of publications, connected with verification and diagnostics of digital devices, today instrumental tools of automatic test generation for complex DD functional verification are actual and claimed. Lack of automatic test generators is felt in many well-known companies: Aldec, Altera, Actel, Xilinx, Synopsis. Thus, this work aim is to develop HDL-models verification strategy, which allows decreasing time on design cycle by decreasing number of test vectors.
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