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|Title:||New features of deductive fault simulation|
|Authors:||Hahanov, V. I.|
Obrizan, V. I.
Kiyaszhenko, A. V.
Pobezhenko, I. A.
deductive fault simulation
|Citation:||Hahanov V. I. New features of deductive fault simulation /V. I. Hahanov, V. I. Obrizan, A. V. Kiyaszhenko, I. A. Pobezhenko //Proceedings of East-West Design & Test Workshop (EWDTW’04)|
|Abstract:||Design Automation Department, Kharkov National University of Radio Electronics, Lenin ave, 14, Kharkiv, 61166 Ukraine. E-mail: email@example.com This paper describes the Fast Backtraced DeductiveParallel Fault Simulation method. This method is oriented on processing large digital devices that are described in RTL or gate level format. Also in article are described data structures and algorithms for implementation of the method in the automated design for test (DFT) systems. The work is conditioned by importance of dramatic improve of test generation speed for complex digital devices implemented in ASICs. Well known automatic test generation and fault simulation systems from such vendors as Cadence, Mentor Graphics, Synopsis, Logic Vision, are oriented on processing of whole logic blocks (chips). But maximum size of such logic blocks is about hundred of thousands of equivalent gates and the processing time is several hours and more. It is not acceptable for today multi-million gates digital designs. Therefore, it is needed to develop new approach to the problem, that allows to speed-up digital system analysis and test generation. To solve this problem the new technology has been used, and the fast fault simulation method have been developed. Unit under test is a digital system, which can be implemented in ASIC. The system is described on HDL. Objectives are to develop high performance stuck-at-fault simulation method for evaluation of quality of generated tests for digital systems. Method should satisfy designers of multi-million gates devices.|
|Appears in Collections:||Кафедра автоматизації проектування обчислювальної техніки (АПОТ)|
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