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Title: Models and Methods for Verification and Diagnosis of SoC HDL-code
Authors: Hahanov, V.
Gharibi, W.
Litvinova, E.
Chumachenko, S.
Keywords: time-to-market
Issue Date: 2010
Publisher: ХНУРЭ
Citation: Models and Methods for Verification and Diagnosis of SoC HDL-code / V. Hahanov and all // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2010. – Вып. 4. – С. 36-46.
Abstract: Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-tomarket of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

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