Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1964
Title: Logic and Fault Simulation Based on Shared-Memory Processors
Authors: Obrizan, Volodymyr
Shipunov, Valeriy
Gavryushenko, Andiry
Kashpur, Oleg
Keywords: Logic
Fault Simulation Based
Shared-Memory Processors
Issue Date: 2006
Publisher: EWDTW
Citation: Volodymyr Obrizan Logic and Fault Simulation Based on Shared-Memory Processors /Volodymyr Obrizan, Valeriy Shipunov, Andiry Gavryushenko, Oleg Kashpur //Proceedings of IEEE East-West Design & Test Workshop (EWDTW’06)
Abstract: Existing software in Electronic Design Automation shows lack of dual-core processors support. As a result, we see bad processing resources utilization. This work-in-progress is devoted to exploration of existing approaches to parallel logic and fault simulation on dual-core workstations. The scale of modern digital system-on-chips continuously increases the complexity of testing during design and manufacturing. It makes the problem of fault simulation and automatic test pattern generation more and more relevant. The performance of fault and fault-free simulation software and the speed of workstations grow noticeably slower, than the structural and functional complexity of digital systems, or the verification cost. In the era of embedded systems, it is easy to create complex devices using system-level approach, but at the same time it is hard to simulate, verify and test such devices. Previously, engineers used highperformance workstations to reduce simulation run time. But nowadays, microprocessors frequencies stop rising, and to solve performance problems, computers enter an era of a multi-core processing. Multiprocessors came to home and office desktops, not only to supercomputer centers. Thus, GHzs don’t determine the performance of the workstation anymore. Also it’s well known, that single-threaded application or serial algorithm (even best optimized for serial processing) shows no expected acceleration on multi-processor systems. In the present days, each application must be designed to gain maximum performance of multi-core architectures. This statement is a baseline of the proposed research. The goal of research – reduce simulation run-time using efficient shared-memory processing. Research tasks: 1) analyze existing algorithms and software products on the subject of serial and parallel data processing; 2) develop parallel algorithms for efficient shared memory utilization; 3) develop software implementation and conduct verification and testing.
URI: http://openarchive.nure.ua/handle/document/1964
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