Please use this identifier to cite or link to this item:
|Title:||High level FSM design transformation using state splitting|
|Keywords:||High level FSM|
|Citation:||Elvira Kulak High level FSM design transformation using state splitting /Eugene Kovalyov, Yevgeniya Syrevitch, Elvira Kulak, Evgeniya Grankova//Proceedings of IEEE East-West Design & Test Workshop (EWDTW’05)|
|Abstract:||One of the problems in the testbench generation for extended finite state machines (EFSM) is existence of internal variables. In fact the usage of these variables in the condition of transition increases real quantity of states by orders. Even for a variable with bit length 20 it leads to the state explosion problem. But for some control unit it is possible to make redesign of the project by including state variables to state register. The transformation algorithm contains phases of state splitting, transition splitting, unreachable (dead) state reduction and equivalent states minimization. The results of such transformation can be used for design analysis, optimization, validation, verification, synthesis and implementation. This paper was motivated by author’s work in the project ASFTest – a testbench generator for Aldec finite state machines. Graphical user interface used in state-of-the-art software allows to create environment for design entry with finite state machine abstract usage. Such form of design description is used in many software and hardware design tools like StatedCAD, FPGA Advantage, Stateworks, Stateflows, etc. The algorithm is described in the graphical way using the extended FSM notation. VHDL is chosen as target language. Synthesis is made by Xilinx synthesis tool which is included in Xilinx Webpack environment. The target device is CPLD Coollrunner II.|
|Appears in Collections:||Кафедра автоматизації проектування обчислювальної техніки (АПОТ)|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.