Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1955
Title: HES-MV – A Method for Hardware Embedded Simulation
Authors: Hahanov, Vladimir
Krasovskaya, Anastasia
Boichuk, Maryna
Gorobets, Oleksandr
Keywords: Multi-valued
software tools
hardware tools
Issue Date: 2006
Publisher: EWDTW
Citation: Vladimir Hahanov HES-MV – A Method for Hardware Embedded Simulation /Vladimir Hahanov, Anastasia Krasovskaya, Maryna Boichuk, Oleksandr Gorobets //Proceedings of IEEE East-West Design & Test Workshop (EWDTW’06)
Abstract: Hardware implementation of triadic fault-free simulation method HES-MV – Hardware Embedded Simulation based on Multi-Valued alphabet is proposed. This method uses hardware gate and RTL models for large scale digital designs description. Structure solutions for logic elements models implementation are presented. Logic element has two bits for four values encoding for each input or output line of simulated device. Necessity for considerable increase of simulation performance for testing and verification purposes is well-known, it is defined by increasing complexity of digital system-on-chips with millions of gates. Existing simulation tools of leading companies: Cadence, Mentor Graphics, Synopsys, Aldec, spend several hours to analyze design with several millions of gates (PC with 500MHz microprocessor and 512MB RAM). Such costs are very important for end users. Aldec Inc. (www.aldec.com) proposes one of the possible solution: during system verification, separate design model on two parts (hardware H and software S): M={H,S}, H>>S. Moreover software model – a new one, unverified source code. Hardware part is tested IP –cores, implemented into HES (Hardware Embedded Simulator), based on Xilinx’s FPGA, connected to the simulation kernel through PCI interface. Thus, Aldec proposed new design flow for world market, it gives possibility to reduce verification time in ten times. But hardware-based simulation excludes possibility for multi-valued simulation mode and transition analysis, hazard simulation, races analysis as well. Proposed approach, along with preserving hardware simulation advantages in performance, allows to simulate signal races and to solve set-up problem by extending hardware model with two-bit signals to identify four states of logic variable. Proposed bus-based primitive and logic elements hardware models may be important on world market of electronic design automation tools for design and test of large scale digital devices. Object of inquiry – digital circuit, implemented into ASIC of PLD, specified using VHDL language. Goal of the research – considerable decrease digital device design time (which will be implemented into integrated circuit, containing millions of gates) and extend functional capabilities of fault-free simulation system by multi-valued models hardware implementation, high-performance simulation method for set-up problem solving, race analysis and timing verification of tests under synthesis. Research problems: 1. Digital circuit models classification. 2. Multi-valued analysis model for hazard detection and set-up problem solving. 3. Creation of software/hardware tools structure to multi-valued fault-free simulation. 4. Software/hardware implementation of multi-valued fault-free simulation method. 5. Testing and verification of hardware/software HES-MV tool.
URI: http://openarchive.nure.ua/handle/document/1955
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

Files in This Item:
File Description SizeFormat 
Хаханов_EWDTW_2006.pdf801.1 kBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.