Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/1905
Title: Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation
Authors: Arabian, J. H.
Keywords: optimization
semiconductors
testing
process
mapping
modeling
Issue Date: 2009
Publisher: ХНУРЭ
Citation: Arabian, J. H. Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation / J. H. Arabian // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 21-23.
Abstract: TESTING of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources. It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.
URI: http://openarchive.nure.ua/handle/document/1905
Appears in Collections:Радиоэлектроника и информатика

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