Analysis of the state diagram correctness of automatic logic control systems on FPGA paper

Abstract

The work is dedicated to verification of automatic logic control systems by analyzing the correctness of state diagrams of control finite state machines which are represented in the form of the code in the hardware description language. As a method for state diagram analysis the, it is proposed to use the concept of orthogonality, as a system of incompatible events. Analysis of the correctness is carried out by analysis the results of behavioral modeling and logical synthesis using CAD tools.