Testable design of control digital automatic machines

Abstract

Abstract—The aim of the work is to analyze hardware costs of ensuring the testability of finite state machines with various options for organizing an additional transition between FSM’s states depending on the presence of an unconditional transition, a conditional transition, and the absence of transitions between states of analyzed FSM. The conclusion on additional hardware costs is made on the basis of a comparison of synthesis results of testable HDL-models by means of CAD FPGA. The paper solved the problem of computer-aided design of testable control FSM based on the application of methods for setting FSM in a given state. The best way to organize additional transitions during setting of control FSM in an arbitrary state is the transition for which the total hardware cost estimate for the excitation functions is minimal, taking into account the coding of FSM’s states.