Створення модуля VHDL-опису при проектуванні цифрових систем на ПЛІС в Xilinx ISE Design Suite

Abstract

When implementing large projects based on modern FPGAs, there are limitations to the circuitry method for describing digital devices, which are removed using high-level languages VHDL and Verilog. These limitations are most noticeable when using FPGA chips. Currently, the main means of representing digital devices in their design are HDL (Hardware Description Language). The use of high-level hardware description languages also increases the mobility of projects under development, since most design systems of various manufacturers support VHDL and Verilog standards.