Synthesis of Qubit Models for Logic Circuits

Zaychenko, S. A.; Gharibi, W.; Dahiri Farid; Hahanova, Yu. V.; Guz, O. A.; Ngene, C. U.; Adiele Stanley

Публікація:
Synthesis of Qubit Models for Logic Circuits

dc.contributor.author	Zaychenko, S. A.
dc.contributor.author	Gharibi, W.
dc.contributor.author	Dahiri Farid
dc.contributor.author	Hahanova, Yu. V.
dc.contributor.author	Guz, O. A.
dc.contributor.author	Ngene, C. U.
dc.contributor.author	Adiele Stanley
dc.date.accessioned	2016-09-06T06:47:18Z
dc.date.available	2016-09-06T06:47:18Z
dc.date.issued	2012
dc.description.abstract	Qubit (quantum) structures of data and computational processes for significantly improving performance when solving problems of discrete optimization and fault-tolerant design are proposed. We describe superpositional method for synthesizing cube of functionality for its implementation in the structural components of programmable logic chips. The estimates of synthesis time, as well as hardware costs for creating qubit models of logic circuits are represented. Quantum computing becomes interesting for cyberspace analysis, creating new Internet technologies and services, which is explained by their alternative to the existing models of computing processes. Market appeal of quantum (qubit) models is based on the high parallelism when solving almost all discrete optimization problems, factoring, minimization of Boolean functions, effective compression of data, their compact representation and teleportation, fault-tolerant design through significant increase in hardware cost. But now it is acceptable, because there are problems of use silicon chip, which contains up to 1 billion gates on a substrate thickness 5 microns. At that modern technologies allow creating a package (sandwich) containing up to 7 chips, which is comparable with the quantity of the human brain neurons. Practically, through-silicon via (TSV) connection is based on the technological capability of drilling about 10 thousand through vias in 1 square centimeter of wafer or die. Layout the indicated volume of useful functionality on chip is currently problematic. So, it is necessary to develop hardwarefocused models and methods for creating high-speed tools of parallel solving real world problems. Considering the discreteness and multiple-valuedness of the alphabets for description of information processes, the parallelism, inherent in the quantum computing, is particularly actual when developing effective and intelligent engines for cyberspace or Internet, tools for synthesis of fault-tolerant digital primitives and systems, testing and simulation of digital systems-on-chips, technologies for information and computer security, brain-like models for computing, analysis and synthesis of linguistic constructions.	uk_UA
dc.identifier.citation	Zaychenko S. A. Synthesis of Qubit Models for Logic Circuits/Wajeb Gharibi, Zaychenko S. A., Dahiri Farid, Hahanova Yu. V., Guz O. A., Ngene Christopher Umerah, Adiele Stanley //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2012)	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/2115
dc.language.iso	en	uk_UA
dc.publisher	EWDTS	uk_UA
dc.subject	Synthesis	uk_UA
dc.subject	Qubit	uk_UA
dc.subject	Logic Circuits	uk_UA
dc.title	Synthesis of Qubit Models for Logic Circuits	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication