Hierarchical Analysis of Testability for SoCs

Kaminska, M.; Hahanov, V. I.; Kulak, E.; Guz, O. A.

Публікація:
Hierarchical Analysis of Testability for SoCs

dc.contributor.author	Kaminska, M.
dc.contributor.author	Hahanov, V. I.
dc.contributor.author	Kulak, E.
dc.contributor.author	Guz, O. A.
dc.date.accessioned	2016-09-02T06:54:44Z
dc.date.available	2016-09-02T06:54:44Z
dc.date.issued	2006
dc.description.abstract	This paper presents the strategy of testable SoC design procedure. This approach based on the testability analysis on different levels of abstractions (gate level, register transfer level, system level). Analysis is based on structural analysis of SoC. Proposed methods give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The main goal of the presented algorithms is to increase fault coverage before test generation and to decrease verification time. It could be reached by improving of testability and simplification of the verification task. As a complexity of today’s ASIC designs continues to increase, the challenge of verifying these designs intensifies at an even greater rate [1]. Testability is one of the most important factors that are considered at digital devices design along with reliability, speed and the cost. The low level of device testability leads to increasing of number of non-tested faults and verification time at design, production and operations stages. Therefore, the cost of diagnostic (a degree of faults concentration) decreases essentially during techniques of testability design. The cost of a fault essentially increases in the process of ASIC crystal implementation (Fig. 1). Hence analysis of testability needs to be done at earlier level of device description. This is the main reason of development of the methods of testability analysis at the different levels of abstraction: system, RT, and gate levels. Object under test – system on chip, which can be presented on different levels of abstraction. Goal of work – maximal decreasing of test procedure cost; to provide digital circuit testability on all design levels of abstraction, till device manufacturing stage. To provide device testing possibility with minimal test by adding of scan cells on bottlenecks in circuit (circuit’s parts, which hard to test).	uk_UA
dc.identifier.citation	Elvira Kulak Hierarchical Analysis of Testability for SoCs /Maryna Kaminska, Vladimir Hahanov, Elvira Kulak, Olesya Guz //Proceedings of IEEE East-West Design & Test Workshop (EWDTW’06)	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1956
dc.language.iso	en	uk_UA
dc.publisher	EWDTW	uk_UA
dc.subject	Hierarchical Analysis	uk_UA
dc.subject	Testability	uk_UA
dc.subject	SoC	uk_UA
dc.title	Hierarchical Analysis of Testability for SoCs	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication