Hahanov, V. I.Litvinova, E. I.Gharibi, W.2016-09-022016-09-022008Hahanov, V. General Testing Models of SOC Hardware Software Components / V. Hahanov, E. Litvinova, W. Gharibi // Radioelektronics & informatics : Scientific and Technical Journal. – Kharkiv, 2008. – Вып. 1 (40). – С. 88–96.http://openarchive.nure.ua/handle/document/1954Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.enInfrastructure Intellectual PropertyRegister Transfer GraphSystem-on-a-ChipTestingArticle