Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/11865
Title: Encoding of Terms in EMB-Based Mealy FSMs
Authors: Barkalov, A.
Titarenko, L.
Mazurkiewicz, M.
Krzywicki, K.
Keywords: mealy finite state machine
synthesis
structural decomposition
FPGA
look-up table elements
LUT
embedded memory blocks
EMB
Issue Date: 2020
Publisher: ХНУРЕ
Citation: Barkalov A., Titarenko L., Mazurkiewicz M., Krzywicki K. Encoding of Terms in EMB-Based Mealy FSMs // Appl. Sci. 2020, 10(8), 2762; https://doi.org/10.3390/app10082762
Abstract: AmethodisproposedtargetingimplementationofFPGA-basedMealyfinitestatemachines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levelsinFSMlogiccircuits. Todoit,itisnecessarytoeliminatethedirectdependenceofinputmemory functions and FSM output functions on FSM inputs and state variables. The method is based on encodingofthetermscorrespondingtorowsofdirectstructuretables. Insuchanapproach,onlyterms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.
URI: http://openarchive.nure.ua/handle/document/11865
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