Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/3917
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dc.contributor.authorHahanov, V.I.-
dc.contributor.authorDahiri, F.-
dc.date.accessioned2017-06-19T10:54:37Z-
dc.date.available2017-06-19T10:54:37Z-
dc.date.issued2014-
dc.identifier.citationHahanov V.I., Dahiri Farid //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2014)uk_UA
dc.identifier.urihttp://openarchive.nure.ua/handle/document/3917-
dc.descriptionAbstract – The processor is implemented in softwarehardware modules, which are based on the use of programming languages: C ++, Verilog, Python 2.7 and platforms: Microsoft Windows, X Window (in Unix and Linux) and Macintosh OS X. HDL-code generator makes it possible to automatically synthesize HDL-code of the processor structure from 1 to 16 bits for parallel processing corresponding number of input vectors or words.uk_UA
dc.language.isoenuk_UA
dc.publisherEWDTSuk_UA
dc.subjectmanipulation algorithmsuk_UA
dc.subjectmatrixuk_UA
dc.titleMatrix Manipulation Algorithms for Hasse Processor Implementationuk_UA
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

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