Please use this identifier to cite or link to this item: http://openarchive.nure.ua/handle/document/2135
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dc.contributor.authorZaychenko, S.-
dc.contributor.authorMelnik, D.-
dc.contributor.authorLukashenko, O.-
dc.date.accessioned2016-09-06T09:05:49Z-
dc.date.available2016-09-06T09:05:49Z-
dc.date.issued2008-
dc.identifier.citationZaychenko S. Verification Challenges of Clock Domain Crossings/D. Melnik, S. Zaychenko, O. Lukashenko//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’08)uk_UA
dc.identifier.urihttp://openarchive.nure.ua/handle/document/2135-
dc.description.abstractThis paper discusses typical verification problems occurring within SoC design cycle when multiple clock domains are involved. Critical cases leading to unpredictable SoC behavior during data transfer across clock domains are identified and described. A principle for metastability modeling is suggested. Only the most elementary logic circuits use a single clock. Today’s system-on-chips (SoC) have dozens of asynchronous clocks. There are a lot of software programs to assist in creating of multimillion-gate ASIC/FPGA circuits, but designer still has to know reliable design techniques to reduce the risk of CDCrelated design re-spins. Moreover, the most relevant literature does not cover CDC-related issues and approaches to prevent appropriate costly silicon bugs.uk_UA
dc.language.isoenuk_UA
dc.publisherEWDTSuk_UA
dc.subjectVerificationuk_UA
dc.subjectClock Domain Crossingsuk_UA
dc.titleVerification Challenges of Clock Domain Crossingsuk_UA
dc.typeArticleuk_UA
Appears in Collections:Кафедра автоматизації проектування обчислювальної техніки (АПОТ)

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