Публікація:
Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation

Завантаження...
Зображення мініатюри

Дата

2009

Автори

Назва журналу

ISSN журналу

Назва тома

Видавництво

ХНУРЭ

Дослідницькі проекти

Організаційні підрозділи

Видання журналу

Анотація

TESTING of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources. It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.

Опис

Ключові слова

optimization, semiconductors, testing, process, mapping, modeling

Бібліографічний опис

Arabian, J. H. Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation / J. H. Arabian // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 21-23.

DOI