Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation

Brinso, M. E.; Nabijou, H.

Публікація:
Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation

dc.contributor.author	Brinso, M. E.
dc.contributor.author	Nabijou, H.
dc.date.accessioned	2016-08-11T10:59:30Z
dc.date.available	2016-08-11T10:59:30Z
dc.date.issued	2009
dc.description.abstract	Mixed-mode simulation is an important circuit design and system testing tool for established and emerging semiconductor sampled data technologies. This paper describes a number of functional, computationally efficient, Z domain delay models, outlining the role of current and charge equations in the construction of subcircuit and compact Verilog-A delay macromodels. To illustrate the properties of the proposed macromodels a number of Qucs (Quite universal circuit simulator) transient and frequency domain simulation examples are presented. Each of these stresses the use of test and data extraction techniques which are not easily undertaken with the SPICE 2g6 or 3f5 simulators.	uk_UA
dc.identifier.citation	Brinson, M. E. Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation / M. E. Brinson, H. Nabijou // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 14-20.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/1810
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	qucs (quite universal circuit simulator)	uk_UA
dc.subject	compact Verilog-A delay macromacromodels	uk_UA
dc.subject	functional delay subcircuits	uk_UA
dc.subject	mixed-mode sampled data circuit simulation	uk_UA
dc.title	Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication