Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation

Øystein Gjermundnes; Einar J. Aas

Публікація:
Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation

dc.contributor.author	Øystein Gjermundnes
dc.contributor.author	Einar J. Aas
dc.date.accessioned	2016-09-05T08:58:26Z
dc.date.available	2016-09-05T08:58:26Z
dc.date.issued	2008
dc.description.abstract	The implementation of a system for analyzing circuits with respect to their path-delay fault testability is presented. It includes a path-delay fault simulator, and an ATPG for path-delay faults combined into a test tool. The test tool is used to evaluate the performance of several different test vector generators. The test generators exploit weighted pseudo-random stimuli generation, based on arithmetic BIST and SIC patterns. The main goal is to find efficient heuristics that improves path-delay fault detection efficiency in terms of test time. We show that weighted ABIST stimuli are productive for detecting the K-longest path-delay faults for most circuits. On the average, we obtained fault coverage of 92.6% for the 20.000 longest paths on iscas’85 circuits. Index Terms − Built-in testing, Fault diagnosis, Automatic testing.	uk_UA
dc.identifier.citation	Gjermundnes, O. Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation/ O. Gjermundnes, E. J. Aas // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 1. – С. 13–18.	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/2078
dc.language.iso	en	uk_UA
dc.publisher	ХНУРЭ	uk_UA
dc.subject	Automatic testing	uk_UA
dc.subject	Fault diagnosis	uk_UA
dc.subject	Built-in testing	uk_UA
dc.title	Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication