Testing and Verification of HDL-models for SoC components

Hahanova, I. V.; Hahanov, V.; Ngene, C. U.; Yves, T.

Публікація:
Testing and Verification of HDL-models for SoC components

dc.contributor.author	Hahanova, I. V.
dc.contributor.author	Hahanov, V.
dc.contributor.author	Ngene, C. U.
dc.contributor.author	Yves, T.
dc.date.accessioned	2016-09-06T07:11:28Z
dc.date.available	2016-09-06T07:11:28Z
dc.date.issued	2009
dc.description.abstract	The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-tomarket) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed. The novel testing and verification technology for system HDL models allows searching for errors in the HDL-code with a given thoroughness for an acceptable time by means of the introduction assertion redundancy to the critical points of the software model, which are defined by the synthesized logic functions of the testability. The controllability and observability criteria, used in hardware design and test, are applied to estimate the quality of software code in order to improve it and effective diagnose semantic errors. The objective is improvement of the testing and verification technology for digital systems to diagnose and correct of errors for HDL-models by sharing of the assertion engine and testable design technologies. The research tasks: 1. Design verification and testing environment for system HDL-model on the basis of assertions. 2. Development of testability evaluation metrics on the basis of new logic testability function. 3. Application of a technological assertion model to verify an IP-core filter on the basis of discrete cosine transform. 4. Practical results and directions for further research. The research sources: 1. Technologies and tools of test and testbench creation are represented in the papers [1-3]. 2. Models and methods for verification of the system models on the basis of assertions are described in [4-7]. Testable software design uses the IEEE standards [8-10], as well as innovative solutions to verify and testability analysis for the system HDLmodels [11-18].	uk_UA
dc.identifier.citation	Hahanova Irina Testing and Verification of HDL-models for SoC components /Vladimir Hahanov, Irina Hahanova, Ngene Christopher Umerah, Tiecoura Yves //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09)	uk_UA
dc.identifier.uri	http://openarchive.nure.ua/handle/document/2120
dc.language.iso	en	uk_UA
dc.publisher	EWDTS	uk_UA
dc.subject	HDL-program	uk_UA
dc.subject	Models and methods for verification	uk_UA
dc.title	Testing and Verification of HDL-models for SoC components	uk_UA
dc.type	Article	uk_UA
dspace.entity.type	Publication